The increasing demand for electronics is driving shorter development cycles for application-specific integrated circuits (ASICs). To meet these constraints, hardware designers emphasize reusability and modularity of IP blocks, leveraging standard system-on-chip (SoC) architectures with integrated processors and common interconnects. While these architectures reduce design and verification efforts, they also introduce complexity, as verification must encompass both hardware and software execution. To enhance reusability, hardware IP blocks are often described in higher-abstraction-level languages such as Chisel and SystemRDL, relying on compilers to generate Verilog for RTL simulation and implementation. At the system level, SoC modeling and verification leverage C++ and SystemC, underscoring the need for software compilation. Consequently, an effective build system must support both hardware design flows and software compilation, including cross-compilation for C++, C, and assembly. Existing hardware build systems lack sufficient support for software compilation, necessitating the development of a new solution. In response, the Microelectronics section of CERN initiated SoCMake, initially as part of the System-on-Chip Radiation Tolerant Ecosystem (SOCRATES). Designed to automate the generation of fault-tolerant RISC-V SoCs for high-energy physics environments, SoCMake has since evolved into a generic open-source build tool for SoC generation.

翻译：电子产品的日益增长需求正推动专用集成电路（ASIC）开发周期不断缩短。为满足这些约束条件，硬件设计者强调IP核的可复用性与模块化，采用集成处理器和通用互连的标准片上系统（SoC）架构。虽然这些架构降低了设计与验证工作量，但也引入了复杂性，因为验证必须同时涵盖硬件执行与软件执行。为提升可复用性，硬件IP核通常采用Chisel和SystemRDL等高抽象层级语言进行描述，依赖编译器生成用于RTL仿真与实现的Verilog代码。在系统层级，SoC建模与验证利用C++和SystemC，凸显了软件编译的必要性。因此，有效的构建系统必须同时支持硬件设计流程与软件编译（包括C++、C及汇编语言的交叉编译）。现有硬件构建系统对软件编译的支持不足，亟需开发新的解决方案。为此，欧洲核子研究中心微电子部门启动了SoCMake项目，最初作为抗辐射片上系统生态系统（SOCRATES）的组成部分。该项目旨在为高能物理环境自动生成容错RISC-V片上系统，现已发展成为通用的开源SoC生成构建工具。