Convolutional Neural Networks (CNNs) have achieved state-of-the-art accuracy in Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR). However, their high computational cost, latency, and memory footprint make its deployment challenging on resource-constrained platforms such as small satellites. While adversarial robustness is critical for real-world SAR ATR, it is often overlooked in system-level optimizations. Achieving both robustness and inference efficiency requires a unified framework that considers adversarially trained models together with hardware constraints. We present a model-hardware co-design framework for CNN-based SAR ATR that integrates robustness-preserving model compression with FPGA accelerator design. The compression stage includes hardware-guided structured pruning, where a hardware performance model derived from the FPGA design predicts the pruning impact on latency and resource usage. This enables the generation of Pareto-optimal models that improve hardware efficiency under user-defined objectives, while maintaining adversarial robustness within a predefined tolerance. We design an FPGA accelerator with channel-aware Processing Element (PE) allocation that supports both fully pipelined streaming and temporal resource-reuse architectures. An automated design generation flow efficiently maps the compressed models to optimized FPGA implementations. Experiments on the widely used MSTAR and FUSAR-Ship datasets across three CNN architectures show that our framework produces models up to 18.3x smaller with 3.1x fewer MACs while preserving robustness. Our FPGA implementation achieves up to 68.1x (6.4x) lower inference latency and up to 169.7x (33.2x) better energy efficiency compared to CPU (GPU) baselines, demonstrating the effectiveness of the proposed co-design framework for robust and efficient SAR ATR on FPGA platforms.

翻译：卷积神经网络（CNN）在合成孔径雷达（SAR）自动目标识别（ATR）任务中已取得最先进的精度。然而，其高昂的计算成本、延迟和内存占用使其在小型卫星等资源受限平台上的部署面临挑战。尽管对抗鲁棒性对于实际SAR ATR系统至关重要，但在系统级优化中常被忽视。要同时实现鲁棒性和推理效率，需要一个统一框架，将对抗训练模型与硬件约束共同考虑。我们提出一个基于CNN的SAR ATR模型-硬件协同设计框架，该框架集成了保持鲁棒性的模型压缩与FPGA加速器设计。压缩阶段包含硬件引导的结构化剪枝，其中源自FPGA设计的硬件性能模型可预测剪枝对延迟和资源使用的影响。这使得能够生成帕累托最优模型，在用户定义的目标下提升硬件效率，同时将对抗鲁棒性保持在预定义容差范围内。我们设计了一种支持通道感知处理单元（PE）分配的FPGA加速器，该加速器同时支持全流水线流式架构和时序资源复用架构。自动化设计生成流程将压缩模型高效映射至优化的FPGA实现。在广泛使用的MSTAR和FUSAR-Ship数据集上，针对三种CNN架构的实验表明，我们的框架生成的模型体积最多缩小18.3倍，乘累加运算（MAC）数量减少3.1倍，同时保持鲁棒性。我们的FPGA实现相比CPU（GPU）基线，推理延迟最多降低68.1倍（6.4倍），能效最多提升169.7倍（33.2倍），证明了所提协同设计框架在FPGA平台上实现鲁棒高效SAR ATR的有效性。