Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. These data types are extensively used in a many application domains, such as big data and SQL applications. This way, Tydi provides a higher-level method for defining interfaces between components as opposed to existing bit and byte-based interface specifications. In this paper, we introduce an open-source intermediate representation (IR) which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi's streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, we have created a grammar, parser, and query system, and paired these with a backend targeting VHDL.

翻译：Tydi 是一项面向数字电路中流式数据流设计的开放规范，它允许设计者通过清晰的数据中心类型来表达复合型和可变长度数据结构如何在流中传输。这些数据类型广泛应用于大数据和SQL应用等众多领域。由此，Tydi 提供了一种比现有基于比特和字节的接口规范更高级的方法来定义组件间的接口。本文介绍了一种开源中间表示（IR），该表示支持声明 Tydi 的类型。该中间表示能以 Tydi 流（称为 Streamlets）作为接口创建和连接组件，还能让综合与仿真后端保留文档等高级信息。类型和 Streamlets 可在多个项目间轻松复用，而 Tydi 的流和类型层次结构可用于定义接口契约，从而有助于大型系统设计时的协作。该中间表示将 Tydi 规范中确立的规则和属性编码化，并以数据中心视角补充面向计算的硬件设计工具。为了支持不同的后端和目标平台，该中间表示专注于表达接口，并补充了由硬件描述语言及其他中间表示描述的行为。此外，本文还提出了一种用于验证输入输出与抽象数据流的测试语法，以及用于替换相互依赖组件的测试语法，这使得行为规范成为可能。为演示该中间表示，我们创建了语法解析器与查询系统，并将其与面向 VHDL 的后端配对。