We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions. Our multiplier achieves up to 50.24% higher accuracy than the best reproduced approximate multiplier in DNNs, with 15.76% smaller area, 25.05% less power consumption, and 3.50% shorter delay. Compared with an exact multiplier, our multiplier reduces the area, power consumption, and delay by 44.94%, 47.63%, and 16.78%, respectively, with negligible accuracy losses. The tested DNN accelerator modules with our multiplier obtain up to 18.70% smaller area and 9.99% less power consumption than the original modules.

翻译：本文提出一种近似乘法器的自动设计优化方法，该方法根据操作数分布最小化平均误差。与深度神经网络中性能最佳的复现近似乘法器相比，我们的乘法器实现了高达50.24%的精度提升，同时面积减小15.76%，功耗降低25.05%，延迟缩短3.50%。与精确乘法器相比，我们的乘法器在面积、功耗和延迟方面分别降低了44.94%、47.63%和16.78%，且精度损失可忽略不计。采用所提出乘法器的深度神经网络加速器模块，其面积和功耗分别比原始模块最多减小18.70%和9.99%。