RISC-V processors encounter substantial challenges in deploying multi-precision deep neural networks (DNNs) due to their restricted precision support, constrained throughput, and suboptimal dataflow design. To tackle these challenges, a scalable RISC-V vector (RVV) processor, namely SPEED, is proposed to enable efficient multi-precision DNN inference by innovations from customized instructions, hardware architecture, and dataflow mapping. Firstly, dedicated customized RISC-V instructions are proposed based on RVV extensions, providing SPEED with fine-grained control over processing precision ranging from 4 to 16 bits. Secondly, a parameterized multi-precision systolic array unit is incorporated within the scalable module to enhance parallel processing capability and data reuse opportunities. Finally, a mixed multi-precision dataflow strategy, compatible with different convolution kernels and data precision, is proposed to effectively improve data utilization and computational efficiency. We perform synthesis of SPEED in TSMC 28nm technology. The experimental results demonstrate that SPEED achieves a peak throughput of 287.41 GOPS and an energy efficiency of 1335.79 GOPS/W at 4-bit precision condition, respectively. Moreover, when compared to the pioneer open-source vector processor Ara, SPEED provides an area efficiency improvement of 2.04$\times$ and 1.63$\times$ under 16-bit and 8-bit precision conditions, respectively, which shows SPEED's significant potential for efficient multi-precision DNN inference.

翻译：RISC-V处理器在部署多精度深度神经网络（DNN）时面临严峻挑战，主要源于其精度支持受限、吞吐量不足及数据流设计欠优。为解决上述问题，本文提出一种可扩展的RISC-V向量处理器（RVV）——SPEED，通过定制指令、硬件架构与数据流映射的创新设计，实现高效多精度DNN推理。首先，基于RVV扩展提出专用定制RISC-V指令，使SPEED能够对4至16比特的处理精度进行细粒度控制；其次，在可扩展模块中集成参数化多精度脉动阵列单元，以增强并行处理能力与数据复用机会；最后，提出一种兼容不同卷积核与数据精度的混合多精度数据流策略，有效提升数据利用率与计算效率。基于TSMC 28nm工艺对SPEED进行综合实现，实验结果表明：在4比特精度条件下，SPEED峰值吞吐量达287.41 GOPS，能效达1339.79 GOPS/W；与开源向量处理器先驱Ara相比，在16比特与8比特精度条件下，SPEED的面积效率分别提升2.04倍与1.63倍，充分展现了其在高效多精度DNN推理领域的显著潜力。