Over the past decade, polar codes have received significant traction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary (2x2) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to attain greater code length flexibility. This paper proposes an unrolled architecture for encoding both systematic and non-systematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary (3x3), or binary-ternary mixed kernels. The proposed scheme exhibits an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide trade-offs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially-pipelined polar encoder of size N=4096 operating at a frequency of 270 MHz gives a throughput of 1080 Gbps. Additionally, a new compiler implemented in Python is given to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.

翻译：过去十年中，极化码获得了广泛关注，并被选为第五代（5G）无线通信系统中控制信道的编码方法。然而，传统极化码仅依赖二元（2x2）内核，这将其码长限制为仅为2的幂次方。为此，多核（MK）极化码被提出作为实现更大码长灵活性的可行解决方案。本文提出了一种用于系统码和非系统码MK极化码编码的展开式架构，能够对采用二元、三元（3x3）或二元-三元混合内核构造的码进行高通量编码。该方案通过支持83种不同码型并提供多种在吞吐量与资源消耗之间权衡的架构，展现了前所未有的灵活性。FPGA实现结果表明，一个工作在270 MHz频率、码长N=4096的部分流水线极化编码器可实现1080 Gbps的吞吐量。此外，本研究还提供了一个用Python实现的新型编译器，可自动生成所需编码器的HDL模块。设计者只需输入所需参数，即可直接获得FPGA实现所需的所有VHDL文件。