With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4x speedup in computation time and 10.1 in delay reduction with 32 threads.

翻译：随着大规模集成电路的发展，电子设计自动化（EDA）工具日益注重效率，并行算法已成为发展趋势。延迟缩减优化是ASIC技术映射的关键因素，而超门技术被证明是EDA工具流程中实现该目标的有效方法。然而，我们观察到增加生成的超门数量虽能降低延迟，但会以计算时间指数级增长为代价。本文提出一种并行超门计算方法，用于解决计算耗时与延迟优化之间的权衡问题。该方法利用输入约束超门模式并行生成候选超门，进而筛选有效超门作为结果。实验结果表明了所提方法的有效性：例如，采用32线程时，该方法可在计算时间上实现4倍加速，同时达成10.1的延迟缩减效果。