As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

翻译：随着ChatGPT等大型语言模型（LLMs）展现出前所未有的机器智能，其在通过自然语言交互辅助硬件工程师实现更高效率逻辑设计方面也表现出色。为评估LLMs辅助硬件设计流程的潜力，本研究尝试构建一个自动化设计环境，探索利用LLMs从自然语言规范生成硬件逻辑设计。为实现更易用、高效的芯片开发流程，我们提出一种基于LLMs的可扩展四阶段零代码逻辑设计框架，无需重新训练或微调。首先，原型系统ChipGPT通过生成提示词驱动LLM输出初始Verilog程序；其次，输出管理器对这些程序进行修正与优化，并归并至最终设计空间；最后，ChipGPT在该空间中搜索目标指标下的最优设计。本评测揭示了LLMs能否针对特定规范，通过自然语言生成正确且完整的硬件逻辑设计。结果表明，相较于先前工作及纯原生LLMs，ChipGPT在可编程性、可控性方面均有提升，并展现出更广阔的设计优化空间。