The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like BCH (Bose-Chaudhuri-Hocquenghem) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This article proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and utilizing pipeline techniques. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. Simulation results indicate that the proposed algorithm not only significantly reduces error correction time but also achieves a noticeable reduction in the hardware overhead of the BCH decoder block compared to similar methods.

翻译：最新一代闪存中晶体管尺寸的缩减导致其设计出现编程与数据擦除问题。因此，确保可靠数据存储已成为这类存储结构面临的重大挑战。为应对该挑战，此类存储器控制器采用BCH（Bose-Chaudhuri-Hocquenghem）码等纠错码。在解码BCH码时，纠错延迟与各子模块硬件需求是两个关键因素。本文提出了一种有效方案以提升纠错速度并优化解码器电路效率：建议对BCH解码器子模块采用并行架构并运用流水线技术。此外，为降低BCH解码器模块硬件需求，引入一种基于XOR共享的算法来消除Chien搜索模块中的冗余门。所提解码器采用VHDL硬件描述语言进行仿真，随后通过Xilinx ISE软件完成综合。仿真结果表明，与同类方法相比，所提算法不仅显著缩短了纠错时间，还实现了BCH解码器模块硬件开销的明显降低。