Polar codes have been selected as the channel coding scheme for control channel in the fifth generation (5G) communication system thanks to their capacity achieving characteristics. However, the traditional polar codes support only codes constructed by binary (2x2) kernel which limits the code lengths to powers of 2. Multi-kernel polar codes are proposed to achieve flexible block length. In this paper, the first combinational decoder for multi-kernel polar codes based on successive cancellation algorithm is proposed. The proposed decoder can decode pure-binary and binary-ternary (3x3) mixed polar codes. The architecture is rate-flexible with the capability of online rate assignment and supports any kernel sequences. The FPGA implementation results reveal that for a code of length N = 48, the coded throughput of 812.1 Mbps can be achieved.

翻译：极化码因其能够达到信道容量的特性，已被选为第五代（5G）通信系统中控制信道的信道编码方案。然而，传统极化码仅支持由二进制（2x2）核构造的码字，这限制了码长只能为2的幂次。为实现灵活的块长度，人们提出了多核极化码。本文首次提出了一种基于连续消除算法的多核极化码组合译码器。该译码器能够对纯二进制和二进制-三进制（3x3）混合极化码进行译码。其架构具有速率灵活性，支持在线速率分配，并能处理任意核序列。FPGA实现结果表明，对于码长N=48的码字，可实现812.1 Mbps的编码吞吐量。