The use of quantum processing units (QPUs) promises speed-ups for solving computational problems. Yet, current devices are limited by the number of qubits and suffer from significant imperfections, which prevents achieving quantum advantage. To step towards practical utility, one approach is to apply hardware-software co-design methods. This can involve tailoring problem formulations and algorithms to the quantum execution environment, but also entails the possibility of adapting physical properties of the QPU to specific applications. In this work, we follow the latter path, and investigate how key figures - circuit depth and gate count - required to solve four cornerstone NP-complete problems vary with tailored hardware properties. Our results reveal that achieving near-optimal performance and properties does not necessarily require optimal quantum hardware, but can be satisfied with much simpler structures that can potentially be realised for many hardware approaches. Using statistical analysis techniques, we additionally identify an underlying general model that applies to all subject problems. This suggests that our results may be universally applicable to other algorithms and problem domains, and tailored QPUs can find utility outside their initially envisaged problem domains. The substantial possible improvements nonetheless highlight the importance of QPU tailoring to progress towards practical deployment and scalability of quantum software.

翻译：量子处理单元（QPU）有望加速计算问题的求解。然而，当前设备受限于量子比特数量，并存在显著缺陷，阻碍了量子优势的实现。为迈向实际应用，一种方法是采用硬件-软件协同设计方法。这不仅涉及根据量子执行环境定制问题表述和算法，还包含调整QPU物理属性以适应特定应用的可能性。本研究沿袭后一路径，探究解决四个核心NP完全问题所需的关键指标（电路深度和门数量）如何随定制硬件属性而变化。结果表明，实现近最优性能与特性未必需要最优量子硬件，而可由更简单的结构满足——这些结构有望在多种硬件方法中实现。通过统计分析技术，我们还发现了一个适用于所有课题问题的底层通用模型。这表明我们的结果可能普遍适用于其他算法和问题领域，且定制QPU可在其最初设想的问题领域之外发挥作用。然而，显著的潜在改进凸显了QPU定制对于推进量子软件实际部署与可扩展性的重要性。