The upcoming integration of AI in the physical layer (PHY) of 6G radio access networks (RAN) will enable a higher quality of service in challenging transmission scenarios. However, deeply optimized AI-Native PHY models impose higher computational complexity compared to conventional baseband, challenging deployment under the sub-msec real-time constraints typical of modern PHYs. Additionally, following the extension to terahertz carriers, the upcoming densification of 6G cell-sites further limits the power consumption of base stations, constraining the budget available for compute ($\leq$ 100W). The desired flexibility to ensure long term sustainability and the imperative energy-efficiency gains on the high-throughput tensor computations dominating AI-Native PHYs can be achieved by domain-specialization of many-core programmable baseband processors. Following the domain-specialization strategy, we present TensorPool, a cluster of 256 RISCV32IMAF programmable cores, accelerated by 16 256 MACs/cycle (FP16) tensor engines with low-latency access to 4MiB of L1 scratchpad for maximal data-reuse. Implemented in TSMC's N7, TensorPool achieves 3643~MACs/cycle (89% tensor-unit utilization) on tensor operations for AI-RAN, 6$\times$ more than a core-only cluster without tensor acceleration, while simultaneously improving GOPS/W/mm$^2$ efficiency by 9.1$\times$. Further, we show that 3D-stacking the computing blocks of TensorPool to better unfold the tensor engines to L1-memory routing provides 2.32$\times$ footprint improvement with no frequency degradation, compared to a 2D implementation.

翻译：将AI集成到6G无线接入网(RAN)物理层(PHY)将能在严苛传输场景下实现更高服务质量。然而，深度优化的AI原生PHY模型相比传统基带具有更高的计算复杂度，这对在当代PHY典型亚毫秒实时约束下的部署提出了挑战。此外，随着太赫兹载波的扩展应用，6G基站密集化进一步限制了基站功耗，将计算预算约束在≤100W以内。通过众核可编程基带处理器的领域专用化，可在保证长期可持续性所需灵活性的同时，实现AI原生PHY中主导的高吞吐张量计算所需的能效提升。基于该领域专用化策略，我们提出TensorPool——由256个RISCV32IMAF可编程核心构成的集群，并配备16个256 MAC/周期（FP16）的张量引擎，可通过低延迟访问4MiB L1暂存器实现最大数据复用。基于台积电N7工艺实现的TensorPool在AI-RAN张量运算中达到3643 MAC/周期（89%张量单元利用率），性能是未配备张量加速的纯核心集群的6倍，同时GOPS/W/mm²能效比提升9.1倍。此外，我们证明采用三维堆叠技术构建TensorPool计算模块以优化张量引擎至L1存储器的路由，相较于二维实现可在不降低工作频率的情况下将芯片面积缩小2.32倍。