This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories without increasing the transistor count of the memory cell itself. In the proposed architecture, adjacent cells within a column are reconfigured in a serial topology, thereby exploiting the stacking effect to suppress leakage current, particularly during hold operation. This architectural modification requires corresponding changes to the addressing and sensing structure of the cache, including adjustments to the column organization and readout path. To evaluate the proposed method, transient simulations were carried out using Keysight ADS. The simulation results show that the proposed architecture reduces leakage power compared with the conventional SRAM interconnection scheme while preserving the use of standard 6T SRAM cells.

翻译：本文提出了一种基于传统6晶体管静态随机存取存储器（6T SRAM）单元串联互连的低功耗缓存架构。该方法旨在不增加存储单元本身晶体管数量的前提下，降低基于SRAM的缓存存储器中的泄漏功耗。在所提出的架构中，同一列内相邻的单元被重新配置为串联拓扑结构，从而利用堆叠效应抑制泄漏电流，特别是在保持操作期间。这一架构性修改需要对缓存的寻址与感知结构进行相应调整，包括列组织方式和读出路径的改动。为评估所提方法，利用Keysight ADS进行了瞬态仿真。仿真结果表明，与传统的SRAM互连方案相比，所提架构在保持使用标准6T SRAM单元的同时，有效降低了泄漏功耗。