We present a device-resident, multi-GPU architecture for the large-scale computational verification of Goldbach's conjecture. In prior work, a segmented double-sieve eliminated monolithic VRAM bottlenecks but remained constrained by host-side sieve construction and PCIe transfer latency. Here we migrate the entire segment generation pipeline to the GPU using shared-memory tiling, leaving per-segment host-device communication small and independent of segment size, and schedule work across devices through a lock-free atomic counter, scaling near-linearly to two GPUs (speedup 2.03 at $N = 10^{12}$). On the same hardware, the architecture is $13.1\times$ faster than its host-coupled predecessor at $N = 10^{10}$. It verifies Goldbach's conjecture to $10^{12}$ in 145 seconds of computation and to $10^{13}$ in 3246 seconds on a single NVIDIA RTX 5090, and to $10^{13}$ in 1577 seconds on a second machine with two. Sieve cost grows as $Nπ(\sqrt{N})$, which we analyse and which sets the practical limit on the design and identifies where further optimisation must act. This version corrects two concurrency defects in the implementation described in version~1: the affected timings are re-measured with the corrected release, the four-GPU results are withdrawn, and the range is re-verified with the corrected release. The source code is open-source, the measurement logs and the tests for both defects are archived with it, and the experiments are reproducible on commercially available hardware.

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