Auto-SPICE is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a long-standing challenge in automating netlist generation for analog circuits within circuit design automation. Automating this workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues. We propose a three-step workflow to overcome current limitations: labeling analog circuits, prompt tuning, and netlist verification. This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity. We open-source this solution for community-driven development.

翻译：Auto-SPICE是首个利用大语言模型（LLMs）全自动生成集成电路仿真程序（SPICE）网表的框架。它解决了电路设计自动化中长期存在的模拟电路网表自动生成难题。自动化此工作流程可加速用于模拟电路设计与验证的微调大语言模型的开发。我们识别了该自动化过程中的关键挑战，并评估了当前最先进大语言模型（特别是GPT-4）的多模态能力以应对这些问题。我们提出一个三步工作流程来克服现有局限：模拟电路标注、提示调优和网表验证。该方法旨在构建从电路原理图图像到SPICE网表的端到端生成器，以攻克精确网表生成这一长期存在的障碍。我们的框架在约2,100张不同复杂度的原理图上进行了测试，显示出显著的性能提升。我们将此解决方案开源，以促进社区驱动的开发。