Static timing analysis (STA) is crucial for Electronic Design Automation (EDA) flows but remains a computational bottleneck. While existing GPU-based STA engines are faster than CPU, they suffer from inefficiencies, particularly intra-warp load imbalance caused by irregular circuit graphs. This paper introduces Warp-STAR, a novel GPU-accelerated STA engine that eliminates this imbalance by orchestrating parallel computations at the warp level. This approach achieves a 2.4X speedup over previous state-of-the-art (SoTA) GPU-based STA. When integrated into a timing-driven global placement framework, Warp-STAR delivers a 1.7X speedup over SoTA frameworks. The method also proves effective for differentiable gradient analysis with minimal overhead.

翻译：静态时序分析（STA）是电子设计自动化（EDA）流程的关键环节，但始终是计算瓶颈。现有基于GPU的STA引擎虽比CPU速度更快，却存在效率低下问题，尤其是不规则电路图导致的线程束内负载不均衡。本文提出Warp-STAR——一种新型GPU加速STA引擎，通过在线程束层级编排并行计算消除该不均衡性。该方法相较先前最先进的（SoTA）GPU-based STA实现2.4倍加速。当集成至时序驱动的全局布局框架时，Warp-STAR相较SoTA框架取得1.7倍加速。该方案在可微梯度分析领域同样展现出低开销高效性。