Systolic arrays are a prominent choice for deep neural network (DNN) accelerators because they offer parallelism and efficient data reuse. Improving the reliability of DNN accelerators is crucial as hardware faults can degrade the accuracy of DNN inferencing. Systolic arrays make use of a large number of processing elements (PEs) for parallel processing, but when one PE is faulty, the error propagates and affects the outcomes of downstream PEs. Due to the large number of PEs, the cost associated with implementing hardware-based runtime monitoring of every single PE is infeasible. We present a solution to optimize the placement of hardware monitors within systolic arrays. We first prove that $2N-1$ monitors are needed to localize a single faulty PE and we also derive the monitor placement. We show that a second placement optimization problem, which minimizes the set of candidate faulty PEs for a given number of monitors, is NP-hard. Therefore, we propose a heuristic approach to balance the reliability and hardware resource utilization in DNN accelerators when number of monitors is limited. Experimental evaluation shows that to localize a single faulty PE, an area overhead of only 0.33% is incurred for a $256\times 256$ systolic array.

翻译：脉动阵列因其并行性和高效数据重用能力，成为深度神经网络加速器的首选架构。提升深度神经网络加速器的可靠性至关重要，因为硬件故障会降低深度神经网络推理的准确性。脉动阵列利用大量处理单元实现并行计算，但当某个处理单元发生故障时，错误会传播并影响后续处理单元的计算结果。由于处理单元数量庞大，对每个处理单元实施基于硬件的运行时监测成本过高。本文提出一种优化脉动阵列中硬件监测器布局的解决方案。我们首先证明，定位单个故障处理单元需要 $2N-1$ 个监测器，并推导出监测器的最优布局。进一步研究表明，在给定监测器数量条件下最小化候选故障处理单元集合的第二类布局优化问题是NP难问题。为此，我们提出一种启发式方法，在监测器数量受限时平衡深度神经网络加速器的可靠性与硬件资源利用率。实验评估表明，对于一个 $256\times 256$ 的脉动阵列，定位单个故障处理单元仅需0.33%的面积开销。