The design of asynchronous circuits typically requires a judicious definition of signals and modules, combined with a proper specification of their timing constraints, which can be a complex and error-prone process, using standard Hardware Description Languages (HDLs). In this paper we introduce Yak, a new dataflow description language for asynchronous bundled data circuits. Yak allows designers to generate Verilog and timing constraints automatically, from a textual description of bundled data control flow structures and combinational logic blocks. The timing constraints are generated using the Local Clock Set methodology and can be consumed by standard industry tools. Yak includes ergonomic language features such as structured bindings of channels undergoing fork and join operations, named value scope propagation along channels, and channel typing. Here we present Yak's language front-end and compare the automated synthesis and layout results of an example circuit with a manual constraint specification approach.

翻译：异步电路的设计通常需要对信号和模块进行精细的定义，并结合其时序约束的恰当规范，而使用标准硬件描述语言（HDL）时，这往往是一个复杂且易出错的过程。本文介绍了Yak，一种面向异步捆绑数据电路的新型数据流描述语言。Yak允许设计者通过捆绑数据控制流结构及组合逻辑模块的文本描述，自动生成Verilog代码和时序约束。其时序约束基于局部时钟集方法生成，可被标准工业工具直接使用。Yak具备符合人体工程学的语言特性，例如支持分叉（fork）与合并（join）操作的结构化通道绑定、沿通道的命名值作用域传播，以及通道类型化。本文展示了Yak的语言前端，并通过示例电路将自动综合与布局结果与手动约束规范方法进行了对比。