Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-long lines (SLLs), incur high delay and consume scarce interposer interconnect resources, often dominating critical paths and complicating physical design. To address this, this work proposes an interconnect-aware logic resynthesis method that restructures the LUT-level netlist to reduce the number of SLLs. The resynthesis engine uses die partitioning information to apply logic resubstitutions, which simplifies local circuit structures and eliminates SLLs. By reducing the number of SLLs early in the design flow, prior to physical implementation, the proposed method shortens critical paths, alleviates pressure on scarce interposer interconnect resources, and improves overall physical design flexibility. We further build a tool flow for multi-die FPGAs by integrating the proposed resynthesis method with packing and placement. Experimental results on the EPFL benchmarks show that, compared with a state-of-the-art framework, the proposed method reduces the number of SLLs by up to 24.8% for a 2-die FPGA and up to 27.38% for a 3-die FPGA. On MCNC benchmarks, our tool flow achieves an average SLL reduction of 1.65% while preserving placement quality. On Koios benchmarks, where fewer removable SLLs exist, several designs still exhibit considerable inter-die edge reductions. Overall, the results confirm that reducing inter-die connections at the logic level is an effective approach for multi-die FPGAs.

翻译：多芯片FPGA使得器件规模能够超越光罩尺寸限制，但同时也引入了跨越芯片边界的严重互连开销。芯片间连接（通常称为超长线）会导致高延迟并消耗稀缺的硅中介层互连资源，常常成为关键路径的主导因素并使物理设计复杂化。为解决这一问题，本文提出一种互连感知的逻辑再综合方法，通过重构LUT级网表来减少超长线数量。该再综合引擎利用芯片分区信息进行逻辑重替换，从而简化局部电路结构并消除超长线。通过在物理实现前的设计流程早期减少超长线数量，所提方法能够缩短关键路径、缓解稀缺中介层互连资源的压力，并提升整体物理设计的灵活性。我们进一步将所提再综合方法与打包及布局工具集成，构建了面向多芯片FPGA的完整工具流程。在EPFL基准测试上的实验结果表明：相较于前沿框架，所提方法在双芯片FPGA上可实现最高24.8%的超长线削减，在三芯片FPGA上可达27.38%。在MCNC基准测试中，我们的工具流程在保持布局质量的同时实现了平均1.65%的超长线削减。在可移除超长线较少的Koios基准测试中，多个设计仍展现出显著的芯片间边线减少。总体而言，实验结果证实了在逻辑层级减少芯片间连接是提升多芯片FPGA性能的有效途径。