As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER targets in chiplet systems requires error-correcting codes (ECC), but incurs energy, area, and throughput overheads. We develop a flow centered around RTL synthesis power and area estimations to support pathfinding of inter-chiplet links under a stringent 10-27 delivered BER target. We synthesize a parameterized Reed-Solomon code with CRC-64 and Go-Back-N retry logic to estimate the correction overhead for different transceiver bit error rates. Results show that ECC can materially change link comparisons under common figures of merit and that CRC+ARQ can reduce the required RS strength (and decoder overhead) at moderate BERs while still meeting stringent delivered-BER targets. We present a CP-SAT-based link assignment formulation that uses these ECC-corrected metrics under reach, delivered-bandwidth, and shoreline constraints in system-level optimization.

翻译：随着基于芯粒的集成技术不断发展，设计者必须在多种短距离片间互连技术中进行选择，这些技术在海岸线带宽密度、面积带宽密度、每比特能耗、传输距离以及原始误码率方面存在显著差异。为满足芯粒系统中严格的传输误码率目标，必须采用纠错码技术，但这会带来能耗、面积和吞吐量方面的开销。我们开发了一种以RTL综合功耗与面积估算为核心的流程，用以支持在10⁻²⁷的严格传输误码率目标下进行芯粒间链路的路径规划。我们综合了参数化的里德-所罗门码，并结合CRC-64校验与Go-Back-N重传逻辑，以估算不同收发器原始误码率下的纠错开销。结果表明，在常用的性能指标下，纠错码会实质性地改变链路方案的比较结果；在中等原始误码率条件下，CRC结合自动重传请求机制能够降低所需的里德-所罗门码纠错强度（及相应的解码器开销），同时仍能满足严格的传输误码率目标。我们提出了一种基于约束规划可满足性理论的链路分配模型，该系统级优化模型在传输距离、传输带宽和海岸线资源约束下，采用了上述经纠错码修正的度量指标。