The growing demand for compute-intensive applications has made multi-chiplet architectures a promising alternative to monolithic designs, offering improved scalability and manufacturing flexibility. However, effectively managing the economic effectiveness remains challenging. Existing cost models either overlook the amortization of compute value over a chip's operational lifetime or fail to evaluate how redundancy strategies, which are widely adopted to enhance yield and fault tolerance, impact long-term cost efficiency. This paper presents a comprehensive cost-effectiveness framework for multi-chiplet architectures, introducing a novel Lifecycle Cost Effectiveness (LCE) metric that evaluates amortized compute costs by jointly optimizing manufacturing expenses and operational lifetime. Our approach uniquely integrates: (1) redundancy-aware cost modeling spanning both intra- and inter-chiplet levels, (2) reliability-driven lifetime estimation, and (3) quantitative analysis of how redundancy configurations on overall economic effectiveness. Extensive trade-off and multi-objective optimization studies demonstrate the effectiveness of the model and reveal essential co-optimization strategies between module and chiplet-level redundancy to achieve cost-efficient multi-chiplet architecture designs.

翻译：随着计算密集型应用需求的日益增长，多芯粒架构因其可扩展性和制造灵活性方面的优势，已成为单芯片设计的一种有前景的替代方案。然而，如何有效管理其经济效益仍然是一个挑战。现有的成本模型要么忽略了芯片在其运行生命周期内计算价值的摊销，要么未能评估广泛用于提高良率和容错能力的冗余策略如何影响长期成本效益。本文提出了一个针对多芯粒架构的综合性成本效益分析框架，引入了一种新颖的生命周期成本效益指标，该指标通过联合优化制造成本和运行寿命来评估摊销后的计算成本。我们的方法独特地整合了：（1）涵盖芯粒内和芯粒间层面的冗余感知成本建模，（2）可靠性驱动的寿命估计，以及（3）冗余配置对整体经济效益影响的定量分析。广泛的权衡研究和多目标优化研究证明了该模型的有效性，并揭示了在模块级和芯粒级冗余之间实现协同优化的关键策略，以实现高成本效益的多芯粒架构设计。