The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMCs 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

翻译：Dadda算法是一种并行结构乘法器，其速度明显快于阵列乘法器（如Booth、Braun、Baugh-Wooley等）。然而，该算法功耗较高且硬件实现需要更多门电路。本文设计了一种基于改进型Dadda算法的乘法器，采用所提出的基于半加法器的进位选择加法器（带二进制转超1转换器）和改进的纹波进位加法器（RCA）。该设计在不同工艺技术（即台积电（TSMC）50nm、90nm和120nm）及不同GHz频率（0.5、1、2和3.33GHz）下进行了仿真。具体而言，采用TSMC 50nm工艺的4位电路在3.33GHz频率下功耗为25uW，延迟为76ps。仿真结果表明，与部分密切相关的研究相比，该设计速度更快、功耗能量效率更高，且实现所需的晶体管数量更少。该设计可成为低功耗低成本数字控制器的理想候选方案。最后，将本设计与文献中的最新相关工作进行了比较。