Approximate computing is a promising approach to reduce the power, delay, and area in hardware design for many error-resilient applications such as machine learning (ML) and digital signal processing (DSP) systems, in which multipliers usually are key arithmetic units. Due to the underlying architectural differences between ASICs and FPGAs, existing ASIC-based approximate multipliers do not offer symmetrical gains when they are implemented by FPGA resources. In this paper, we propose AMG, an open-source automated approximate multiplier generator for FPGAs driven by Bayesian optimization (BO) with parallel evaluation. The proposed method simplifies the exact half adders (HAs) for the initial partial product (PP) compression in a multiplier while preserving coarse-grained additions for the following accumulation. The generated multipliers can be effectively mapped to lookup tables (LUTs) and carry chains provided by modern FPGAs, reducing hardware costs with acceptable errors. Compared with 1167 multipliers from previous works, our generated multipliers can form a Pareto front with 28.70%-38.47% improvements in terms of the product of hardware cost and error on average. All source codes, reproduced multipliers, and our generated multipliers are available at https://github.com/phyzhenli/AMG.

翻译：近似计算是一种有前景的方法，可在许多容错应用（如机器学习（ML）和数字信号处理（DSP）系统）中降低硬件设计的功耗、延迟和面积，其中乘法器通常是关键算术单元。由于ASIC与FPGA在底层架构上的差异，基于ASIC的现有近似乘法器在使用FPGA资源实现时无法获得对称的增益。本文提出AMG，一种基于贝叶斯优化（BO）并支持并行评估的开源自动化近似乘法器生成器，专为FPGA设计。所提方法简化了乘法器中初始部分积（PP）压缩的精确半加器（HA），同时保留后续累加中的粗粒度加法。生成的乘法器可有效映射到现代FPGA提供的查找表（LUT）和进位链，在可接受误差下降低硬件成本。与先前工作中的1167个乘法器相比，本文生成的乘法器在硬件成本与误差乘积方面平均可形成帕累托前沿，实现28.70%-38.47%的改进。所有源代码、复现的乘法器及本文生成的乘法器均可在 https://github.com/phyzhenli/AMG 获取。