Floorplanning determines the coordinate and shape of each module in Integrated Circuits. With the scaling of technology nodes, in floorplanning stage especially 3D scenarios with multiple stacked layers, it has become increasingly challenging to adhere to complex hardware design rules. Current methods are only capable of handling specific and limited design rules, while violations of other rules require manual and meticulous adjustment. This leads to labor-intensive and time-consuming post-processing for expert engineers. In this paper, we propose an all-in-one deep reinforcement learning-based approach to tackle these challenges, and design novel representations for real-world IC design rules that have not been addressed by previous approaches. Specifically, the processing of various hardware design rules is unified into a single framework with three key components: 1) novel matrix representations to model the design rules, 2) constraints on the action space to filter out invalid actions that cause rule violations, and 3) quantitative analysis of constraint satisfaction as reward signals. Experiments on public benchmarks demonstrate the effectiveness and validity of our approach. Furthermore, transferability is well demonstrated on unseen circuits. Our framework is extensible to accommodate new design rules, thus providing flexibility to address emerging challenges in future chip design. Code will be available at: https://github.com/Thinklab-SJTU/EDA-AI

翻译：布局规划决定了集成电路中每个模块的坐标与形状。随着工艺节点的微缩，在布局规划阶段，尤其是在具有多层堆叠结构的三维场景中，遵循复杂的硬件设计规则已变得日益困难。现有方法仅能处理特定且有限的设计规则，而其他规则的违反仍需依赖人工进行细致调整，导致专家工程师需要投入大量人力与时间进行后处理。本文提出一种基于深度强化学习的全集成方法以应对这些挑战，并针对先前方法未涉及的实际集成电路设计规则设计了新颖的表征形式。具体而言，我们将各类硬件设计规则的处理统一到一个包含三个关键组件的框架中：1）用于建模设计规则的新型矩阵表征；2）对动作空间的约束以筛除导致规则违反的无效动作；3）将约束满足度的量化分析作为奖励信号。在公开基准测试上的实验验证了本方法的有效性与正确性。此外，该方法在未见电路上亦展现出良好的可迁移性。本框架具有良好的可扩展性，能够兼容新的设计规则，从而为应对未来芯片设计中的新兴挑战提供了灵活性。代码发布地址：https://github.com/Thinklab-SJTU/EDA-AI