Aiming at designing plausible decoders with channel information free, low complexity, high throughput, and approaching maximum likelihood performance, we put forward a streamlined architecture which concatenates sequentially three components. Specifically, to tackle the decoding failures of normalized min-sum, the whole decoding trajectory, not limited to the last iteration information conventionally, is fed into a trained convolutional neural network to yield new reliability metric for each sequence bit, termed decoding information aggregation. Then an adapted order statistics decoding, following the suggested decoding path, is adopted to process the sequence ordered with new metric more efficiently in that many invalid searches contained in conventional methods otherwise are evaded. The role of decoding information aggregation is elaborated via statistics data to reveal that it can arrange more error-prone bits into the fore part of most reliable basis of order statistics decoding, which is vital for the effective decoding enhancement. We argue the superposition of improved bitwise reliability of the most reliable basis and the imposed rigorous code structure by OSD enables the proposed architecture being a competitive rival of the state of the art decoders, which was verified in extensive simulation in terms of performance, complexity and latency for short and moderate LDPC codes.

翻译：针对设计无信道信息、低复杂度、高吞吐量且逼近最大似然性能的实用译码器，我们提出了一种依次串联三个组件的精简架构。具体而言，为应对归一化最小和译码的失败情况，将整个译码轨迹（而非传统上仅限最后一次迭代信息）输入训练好的卷积神经网络，为每个码字比特生成新的可靠性度量，称为译码信息聚合。随后，按照建议的译码路径，采用改进的有序统计译码处理按新度量排序的序列，从而有效规避传统方法中大量无效搜索。通过统计数据阐明译码信息聚合的作用机制：其可将更易出错的比特排列至有序统计译码最可靠基的前端，这对实现有效的译码增强至关重要。我们论证了最可靠基的改进比特可靠性与有序统计译码施加的严格码结构之间的叠加效应，使得所提架构成为现有最优译码器的有力竞争者。针对短码和中长LDPC码的全面仿真验证了该方案在性能、复杂度和时延方面的优势。