This paper introduces Hardcaml, an embedded hardware design domain specific language (DSL) implemented in the OCaml programming language. Unlike high level synthesis (HLS), Hardcaml allows for low level control of the underlying hardware for maximum productivity, while abstracting away many of the tedious aspects of traditional hardware definition languages (HDLs) such as Verilog or VHDL. The richness of OCaml's type system combined with Hardcaml's fast circuit elaboration checks reduces the chance of user-introduced bugs and erroneous connections with features like custom type defining, type-safe parameterized modules and elaboration-time bit-width inference and validation. Hardcaml tooling emphasizes fast feedback through simulation, testing, and verification. It includes both a native OCaml cycle-accurate and an event-driven simulator. Unit tests can live in the source code and include digital ASCII waveforms representing the simulator's output. Hardcaml also provides tools for SAT proving and formal verification. Hardcaml is industrially proven, and has been used at Jane Street internally for many large FPGA designs. As a case study we highlight several aspects of our recent Hardcaml submission to the 2022 ZPrize cryptography competition which won 1st place in the FPGA track.

翻译：本文介绍Hardcaml——一种基于OCaml编程语言实现的嵌入式硬件设计领域专用语言（DSL）。与高层次综合（HLS）不同，Hardcaml允许对底层硬件进行低层级控制以实现最高生产力，同时抽象了传统硬件描述语言（HDL，如Verilog或VHDL）中许多繁琐的方面。OCaml类型系统的丰富性结合Hardcaml的快速电路细化检查，通过自定义类型定义、类型安全参数化模块以及细化时位宽推断与验证等功能，降低了用户引入错误和错误连接的风险。Hardcaml工具链强调通过仿真、测试与验证实现快速反馈，包含原生OCaml周期精确仿真器和事件驱动仿真器。单元测试可嵌入源代码中，并包含代表仿真器输出的数字ASCII波形。Hardcaml还提供SAT求解验证与形式化验证工具。该语言已在工业环境中验证，并长期用于Jane Street内部多个大型FPGA设计。作为案例研究，我们重点介绍了近期提交至2022年ZPrize密码学竞赛的Hardcaml方案在FPGA赛道荣获第一名所体现的若干特性。