Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges {\em all at once}, and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Rather than relying on specialized hardware for syndrome decoding, our system uses a dedicated multi-core CPU for both qubit control and classical computation, including syndrome decoding. This simplifies the system design and facilitates load-balancing between the quantum and classical components. We implement recent proposals as decoding firmware on a RISC-V system-on-chip (SoC) that parallelizes general inner decoders. By using our in-house Union-Find and PyMatching 2 implementations, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available SoCs, under realistic and optimistic assumptions of physical error rate $p=0.001 and p=0.0001, respectively, all in just 1 \textmu s.

翻译：规模扩展是数字量子计算机实现的关键瓶颈，给量子与经典组件均带来挑战。我们提出了一种经典架构，可一次性解决后者涉及的全面挑战，并通过集成多核RISC-V CPU与自研控制电子器件，在以端到端方式实现的系统中完整部署该架构。该架构支持对大型量子处理器进行可扩展、高精度控制，并能够适应量子硬件不断演进的诉求。其核心特性在于一种微架构，可在任意预定义的量子比特组上并行执行量子操作；另一关键特性则是可重构量子指令集，支持便捷的量子比特重组与指令扩展。作为演示，我们实现了被广泛研究的表面码量子计算工作流——该案例因对控制器和集成经典计算均具有高要求而富有指导意义。本设计首次将指令发送与传输成本降低至常数级别（不随量子比特数扩展），且未增加解码或调度开销。不同于依赖专用硬件进行综合征解码，我们的系统采用专用多核CPU同时承担量子比特控制与经典计算（包括综合征解码），从而简化系统设计并促进量子-经典组件间的负载均衡。我们将近期提出的方案作为解码固件部署于RISC-V系统级芯片（SoC）上，该芯片可并行化通用内部解码器。通过采用自研的Union-Find与PyMatching 2实现，在物理错误率分别设为$p=0.001$和$p=0.0001$的现实与乐观假设下，我们仅需1微秒即可利用现有SoC实现最高距离47与67的前所未有解码能力。