Spatial dataflow architectures such as reconfigurable dataflow accelerators (RDA) can provide much higher performance and efficiency than CPUs and GPUs. In particular, vectorized reconfigurable dataflow accelerators (vRDA) in recent literature represent a design point that enhances the efficiency of dataflow architectures with vectorization. Today, vRDAs can be exploited using either hardcoded kernels or MapReduce languages like Spatial, which cannot vectorize data-dependent control flow. In contrast, CPUs and GPUs can be programmed using general-purpose threaded abstractions. The ideal combination would be the generality of a threaded programming model coupled with the efficient execution model of a vRDA. We introduce Revet: a programming model, compiler, and execution model that lets threaded applications run efficiently on vRDAs. The Revet programming language uses threads to support a broader range of applications than Spatial's parallel patterns, and our MLIR-based compiler lowers this language to a generic dataflow backend that operates on streaming tensors. Finally, we show that mapping threads to dataflow outperforms GPUs, the current state-of-the-art for threaded accelerators, by 3.8x.

翻译：空间数据流架构（如可重构数据流加速器RDA）相比CPU和GPU能提供更高的性能与效率。近年来文献中提出的向量化可重构数据流加速器（vRDA）代表了一种通过向量化增强数据流架构效率的设计方向。当前，vRDA可通过硬编码内核或类似Spatial的MapReduce语言来开发，但这类语言无法对数据依赖的控制流进行向量化。相比之下，CPU和GPU可采用通用线程化抽象进行编程。理想的结合方案应融合线程化编程模型的通用性与vRDA的高效执行模型。我们提出Revet：一种让线程化应用高效运行在vRDA上的编程模型、编译器及执行模型。Revet编程语言通过线程支持比Spatial并行模式更广泛的应用场景，我们基于MLIR的编译器将该语言降级至面向流式张量操作的通用数据流后端。最后，实验表明，将线程映射到数据流架构上，其性能比当前线程加速器领域的先进方案GPU高出3.8倍。