We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a Field Programmable Gate Array (FPGA) platform. Our FPGA implementation eliminates the need for DSP units and reduces the number of LUTs. By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from the MP approximation. Using the FPGA platform, we also show that the proposed multiplierless MP-kernel machine demonstrates superior performance in terms of power, performance, and area compared to other comparable implementations.

翻译：我们提出了一个设计无倍数内核机器的新框架,可用于智能边缘装置等资源受限制的平台。框架使用基于边距传播技术的片断线性近似(PWL)近似,仅使用增/减法、转换、比较和内流/流流流操作登记。我们提议了一个基于基于软硬件的基于MP的推论和在线培训算法,该算法已经为外地可编程门阵列(FPGA)平台优化。我们的FPGA实施消除了对DSP单元的需求并减少了LUT的数量。通过重新使用相同的硬件进行推断和培训,我们表明该平台可以克服由于MP近似而出现的分类错误和本地微型工艺。我们使用FPGA平台还表明,拟议的无倍式MP内核机器在能力、性能和面积方面与其他可比较的实施相比,表现优。