The thesis investigates the utilization of memristive and memcapacitive crossbar arrays in low-power machine learning accelerators, offering a comprehensive co-design framework for deep neural networks (DNN). The model, implemented through a hybrid Python and PyTorch approach, accounts for various non-idealities, achieving exceptional training accuracies of 90.02% and 91.03% for the CIFAR-10 dataset with memristive and memcapacitive crossbar arrays on an 8-layer VGG network. Additionally, the thesis introduces a novel approach to emulate meminductor devices using Operational Transconductance Amplifiers (OTA) and capacitors, showcasing adjustable behavior. Transistor-level simulations in 180 nm CMOS technology, operating at 60 MHz, demonstrate the proposed meminductor emulator's viability with a power consumption of 0.337 mW. The design is further validated in neuromorphic circuits and CNN accelerators, achieving training and testing accuracies of 91.04% and 88.82%, respectively. Notably, the exclusive use of MOS transistors ensures the feasibility of monolithic IC fabrication. This research significantly contributes to the exploration of advanced hardware solutions for efficient and high-performance machine-learning applications.

翻译：本论文研究了忆阻和忆电容交叉阵列在低功耗机器学习加速器中的应用，提出了一个面向深度神经网络(DNN)的协同设计框架。该模型采用Python与PyTorch混合编程实现，充分考虑了各种非理想特性，在8层VGG网络上分别使用忆阻和忆电容交叉阵列对CIFAR-10数据集实现了90.02%和91.03%的卓越训练精度。此外，论文还提出了一种利用运算跨导放大器(OTA)和电容模拟忆感器设备的新方法，展示了可调节的动态行为。采用180 nm CMOS技术在60 MHz下进行的晶体管级仿真表明，所提出的忆感器模拟器方案功耗仅为0.337 mW，具备可行性。该设计在神经形态电路和CNN加速器中进一步得到验证，分别实现了91.04%的训练精度和88.82%的测试精度。值得注意的是，全MOS晶体管的采用确保了单芯片集成电路制造的可行性。本研究为探索高效能机器学习应用的先进硬件解决方案做出了重要贡献。