To understand and improve DRAM performance, reliability, security and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limit the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programming interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to (i) support existing and emerging DRAM interfaces, and (ii) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncovers a larger set of bit-flips on a victim row compared to the data patterns commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-Bender.

翻译：为理解和改善DRAM的性能、可靠性、安全性与能效，先前工作研究了商用DRAM芯片的特性。然而，当前能够开展此类研究的先进开源基础设施存在过时、支持不足、使用困难或灵活性受限等问题，限制了可开展的研究类型。我们提出DRAM Bender——一种新型基于FPGA的基础设施，能够对最先进的DRAM芯片进行实验研究。DRAM Bender同时提供三大关键特性：其一，能通过底层接口直接与DRAM芯片交互，相比其他开源基础设施，允许用户以任意顺序及更细粒度的时间间隔发出DRAM命令；其二，提供易用的C++与Python编程接口，使用户能快速便捷地开发不同类型的DRAM实验；其三，具备高度可扩展性。其模块化设计使其可轻松扩展至（i）支持现有及新兴DRAM接口，以及（ii）以极小工作量运行于新型商用或定制FPGA开发板上。为验证DRAM Bender作为多功能基础设施的效能，我们开展三项案例研究，其中两项揭示了DRAM RowHammer漏洞的新特征。特别地，我们证明DRAM Bender支持的数据模式能在受害行上发现比先前工作常用数据模式更广泛的比特翻转现象。通过分别在五款支持DDR4与DDR3的FPGA上实现DRAM Bender，我们展示了其可扩展性。DRAM Bender已在https://github.com/CMU-SAFARI/DRAM-Bender 上免费开源发布。