We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.

翻译：我们提出了一种可扩展的神经形态架构，该架构基于无时钟（异步）数字电路自主时间连续演化产生的脉冲动力学。该系统在商用现场可编程门阵列（FPGA）上实现，构建了具有可配置兴奋性和抑制性突触权重的布尔脉冲神经元交互网络。完整的处理流水线能够高效处理脉冲编码数据以解决机器学习任务。我们展示了在基于脉冲编码的音频分类任务中的竞争性性能与高速处理能力。其功耗显著低于传统数字实现方案；这使我们的方法成为一种连接专用模拟神经形态系统的高效替代方案，且无需专用硬件设计。更广泛而言，本方法确立了无时钟数字硬件作为神经形态计算的可行平台，为将可重构芯片转化为高能效准模拟神经形态处理器铺平了道路。