Layout synthesis is mapping a quantum circuit to a quantum processor. SWAP gate insertions are needed for scheduling 2-qubit gates only on connected physical qubits. With the ever-increasing number of qubits in NISQ processors, scalable layout synthesis is of utmost importance. With large optimality gaps observed in heuristic approaches, scalable exact methods are needed. While recent exact and near-optimal approaches scale to moderate circuits, large deep circuits are still out of scope. In this work, we propose a SAT encoding based on parallel plans that apply 1 SWAP and a group of CNOTs at each time step. Using domain-specific information, we maintain optimality in parallel plans while scaling to large and deep circuits. From our results, we show the scalability of our approach which significantly outperforms leading exact and near-optimal approaches (up to 100x). For the first time, we can optimally map several 8, 14, and 16 qubit circuits onto 54, 80, and 127 qubit platforms with up to 17 SWAPs. While adding optimal SWAPs, we also report near-optimal depth in our mapped circuits.

翻译：布局综合是将量子电路映射到量子处理器的过程。为了在仅连接物理量子比特上调度双量子比特门，需要插入SWAP门。随着NISQ处理器中量子比特数量的持续增长，可扩展的布局综合变得至关重要。鉴于启发式方法中存在显著的最优性差距，亟需可扩展的精确方法。尽管近期精确和近最优方法已能处理中等规模的电路，但大型深度电路仍超出其能力范围。本文提出了一种基于并行规划的SAT编码方法，每个时间步可执行1个SWAP操作和一组CNOT门。通过利用领域特定知识，我们在保持并行规划最优性的同时，将方法扩展至大型深度电路。实验结果表明，该方法具有显著的可扩展性，性能远超主流精确和近最优方法（最高提升100倍）。我们首次实现了将若干8、14、16量子比特电路最优映射至54、80、127量子比特平台，且SWAP门数量不超过17个。在添加最优SWAP的同时，映射电路也实现了近最优深度。