Integrated Circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of Hardware Trojans, can give an adversary access to privileged data and/or the means to corrupt the IC's internal computation. Post-fabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account and at the same time, this paper proposes a methodology for Security-Aware Layout Synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power-performance-area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the trade-offs between PPA and security are considered and a chip is fabricated in a 65nm CMOS commercial technology for validation purposes - a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power in order to achieve significantly improved security metrics.

翻译：集成电路（IC）在其生命周期中面临多种攻击。制造阶段攻击（如硬件木马的植入）可使攻击者获取特权数据和/或篡改IC内部计算。后制造阶段攻击中，终端用户扮演恶意角色，也试图通过故障注入和探针探测等手段获取特权信息。针对这些威胁，本文提出了一种安全感知布局综合（SALSy）方法，使得IC设计能够像当前考虑功耗-性能-面积（PPA）指标一样以安全为导向——这一概念称为安全收敛。此外，本文还权衡了PPA与安全性之间的折衷，并采用65nm CMOS商用工艺流片验证——这一特性在以往安全收敛研究中未曾出现。实测结果表明，SALSy以适度的功耗增加换取了显著提升的安全指标。