This paper introduces a versatile, multi-layered technology to help support teaching and learning core computer architecture concepts. This technology, called CodeAPeel is already implemented in one particular form to describe instruction processing in compiler, assembly, and machine layers of a generic instruction set architecture by a comprehensive simulation of its fetch-decode-execute cycle as well as animation of the behavior of its CPU registers, RAM, VRAM, STACK memories, various control registers, and graphics screen. Unlike most educational CPU simulators that simulate a real processor such as MIPS or RISC-V, CodeAPeel is designed and implemented as a generic RISC instruction set architecture simulator with both scalar and vector instructions to provide a dual-mode processor simulator as described by Flynn's classification of SISD and SIMD processors. Vectorization of operations is built into the instruction repertoire of CodeAPeel, making it straightforward to simulate such processors with powerful vector instructions.

翻译：本文介绍了一种多层次的多功能技术,以帮助支持教学和学习核心计算机结构概念。这种技术称为CodeAPeel, 已经以一种特定的形式应用,通过全面模拟其抓取-decode-Execute 循环以及其CPU登记册、RAM、VRAM、STACK记忆、各种控制登记册和图形屏幕的行为动画,来描述通用指令结构结构的编译、组和机层的教学处理。与大多数模拟像MIPS或RISC-V这样的真实处理器的教育性CPU模拟器不同, CodeAPeel被设计和实施成一个通用的RISC指令结构模拟器,带有标度和矢量指示,以提供Flyn SISD 和 SIMD 处理器分类所描述的双模处理模拟器。 操作的矢量演算器被纳入了代码APeel 的指令汇编,使得用强大的矢量指示来模拟这类处理器变得简单。