Hardware aging poses a significant challenge for integrated circuits (ICs), leading to performance degradation and eventual failure. In this work, we focus on the aging of arithmetic multipliers, which are a cornerstone of modern computing systems including in CPUs, GPUs, and FPGAs, as well as AI accelerators like systolic arrays. In particular, AI workloads, which rely predominantly on multiplications, can accelerate Negative Bias Temperature Instability (NBTI) effects in multipliers. This paper presents a novel aging mitigation technique that leverages the signinvariance property of multiplication. By selectively applying 2s complement transformations to inputs, the method redistributes stress across transistors, reducing the effects of NBTI aging. The proposed method is also integrated into systolic arrays, a common AI accelerator, to demonstrate its efficiency in a high-throughput AI accelerator. Experimental evaluations using Cadence tools show better lifetime compared to natural aging (with no mitigation) baseline, while introducing negligible area and delay overheads.

翻译：硬件老化对集成电路（IC）构成重大挑战，会导致性能退化并最终失效。本文聚焦于算术乘法器的老化问题——作为现代计算系统的基石，乘法器广泛应用于CPU、GPU、FPGA以及脉动阵列等AI加速器中。特别地，以乘法运算为主导的AI工作负载会加速乘法器中负偏置温度不稳定性（NBTI）效应。本文提出一种新颖的老化缓解技术，利用乘法的符号不变性，通过选择性地对输入应用2的补码变换，重新分配晶体管承受的应力，从而降低NBTI老化的影响。该方法还被集成到脉动阵列（一种常见的AI加速器）中，以展示其在高通量AI加速器中的有效性。采用Cadence工具进行的实验评估表明，与自然老化（无缓解）基线相比，该方法在引入可忽略的面积和延迟开销的同时，实现了更优的寿命表现。