Stability of ultra-low-voltage SRAM bitcells in retention mode is threatened by two types of uncertainty: process variability and intrinsic noise. While variability dominates the failure probability, noise-induced bit flips in weakened bitcells lead to dynamic instability. We study both effects jointly in a unified SPICE simulation framework. Starting from a synthetic representation of process variations introduced in a previous work, we identify the cases of poor noise immunity that require thorough noise analyses. Relying on a rigorous and systematic methodology, we simulate them in the time domain so as to emulate a true data retention operation. Short times to failure, unacceptable for a practical ultra-low-power memory system application, are recorded. The transient bit-flip mechanism is analysed and a dynamic failure criterion involving the unstable point is established. We conclude that, beyond static variability, the dynamic noise inflates defectiveness among SRAM bitcells. We also discuss the limits of existing analytical formulas from the literature, which rely on a linear near-equilibrium approximation of the SRAM dynamics to, inaccurately, predict the mean time to failure.

翻译：超低电压SRAM单元在保持模式下的稳定性受到两种不确定性的威胁：工艺变异和固有噪声。虽然工艺变异主导了失效概率，但弱化单元中噪声诱发的位翻转会导致动态不稳定性。我们在统一的SPICE仿真框架中联合研究了这两种效应。从先前工作中引入的工艺变异的综合表示入手，我们识别出需要深入噪声分析的低噪声抗扰性情况。依托严谨系统的方法论，我们在时域中对其进行仿真，以模拟真实的数据保持操作。记录到实际超低功耗存储器系统应用中不可接受的短失效时间。分析了瞬态位翻转机制，并建立了涉及不稳定点的动态失效判据。我们得出结论：除静态变异外，动态噪声加剧了SRAM单元中的缺陷率。我们还讨论了现有文献中解析公式的局限性，这些公式依赖于SRAM动力学的线性近平衡近似来预测平均失效时间，但结果不准确。