Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. However, while these language features significantly improve the process of writing code, debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer. This work, Tywaves, presents a new type-centered debugging format that brings the same level of abstraction found in contemporary hardware languages to waveform viewers. Contributions to the Chisel library and CIRCT MLIR compiler as well as the Surfer waveform viewer result in a waveform viewer that better supports the Chisel HDL. Project url: https://github.com/rameloni/tywaves-chisel-demo

翻译：Chisel（基于Scala嵌入式语言的硬件构造语言）是一种广泛采用的硬件描述语言，它将面向对象与函数式编程、类型安全以及参数化等特性引入硬件设计。然而，尽管这些语言特性显著改善了代码编写过程，但使用开源工具调试Chisel设计时却丧失了源语言的诸多优势——类型信息与数据结构层次在转换、模拟器输出及波形查看过程中均会丢失。本研究提出的Tywaves展示了一种新型以类型为中心的调试格式，将当代硬件语言中的抽象层级引入波形查看器。通过对Chisel库、CIRCT MLIR编译器以及Surfer波形查看器的改进，最终实现了一款能更好支持Chisel硬件描述语言的波形查看器。项目地址：https://github.com/rameloni/tywaves-chisel-demo