Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language. This process often requires significant interpretation by engineers to convert these specifications into functional verification assertions. Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging the practical application. In this work, we present AssertLLM, an automatic assertion generation framework for complete specification files. AssertLLM breaks down the complex task into three phases, incorporating three customized Large Language Models (LLMs) for extracting structural specifications, mapping signal definitions, and generating assertions. Additionally, we provide an open-source benchmark for assessing assertion generation capabilities. Our evaluation of AssertLLM on a full design, encompassing 23 signals, demonstrates that 89% of the generated assertions are both syntactically and functionally accurate.

翻译：基于断言的验证（Assertion-Based Verification, ABV）是确保设计电路符合其架构规格（通常以自然语言描述）的关键方法。该过程通常需要工程师进行大量解读，才能将这些规格转化为功能验证断言。现有从自然语言规格生成断言的方法受限于工程师提取的句子，阻碍了实际应用。本文提出AssertLLM，一种针对完整规格文件的自动断言生成框架。AssertLLM将复杂任务分解为三个阶段，集成三个定制化大型语言模型（Large Language Models, LLMs），分别用于提取结构规格、映射信号定义以及生成断言。此外，我们提供了一个开源基准测试，用于评估断言生成能力。我们在包含23个信号的完整设计上对AssertLLM进行评估，结果表明89%的生成断言在语法和功能上均准确无误。