Logic and fabrication advancements have renewed interest in superconductor electronics for energy-efficient computing and quantum control processors. One of the most challenging obstacles ahead is the lack of a scalable superconducting memory technology. Here, we present a superconducting delay line memory based on Passive Transmission Lines built with high kinetic inductors. The developed memory system is fully superconducting; operates at speeds ranging from 20~GHz to 100~GHz with $\pm$24\% and $\pm$13\% bias margins, respectively; and exhibits data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Moreover, its circulating nature allows the miniaturization of control circuitry, the elimination of data splitting and merging, and the inexpensive implementation of both sequential-access and content-addressable memories. Further advancements to high kinetic inductor fabrication processes indicate even greater data densities of 100s of Mbit/cm$^2$ and beyond.

翻译：逻辑和制造进步使人们对超级导体电子进行高能效计算和量控处理器的兴趣重新增加。前面最困难的障碍之一是缺乏可缩放的超导内存技术。在这里,我们展示了以高动能感应器建造的被动传输线为基础的超导延缓线内存。发达的记忆系统完全超导;运行速度从20~GHz到100~GHz,分别是每24美元和每13美元差幅;以及麻省理工林肯实验室SC2制造工艺的10兆比特/每米2美元显示数据密度。此外,其流通性质使得控制电路的微型化、消除数据分割和合并,以及以廉价方式实施连续获取和内容可处理的记忆。高导电导器制造过程的进一步发展表明100兆比特/每平方美元以上的数据密度更高。