Triggerless Data Acquisition Systems (DAQs) require transmitting the data stream from multiple links to the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network's operation enabled increased scalability compared to the previously published concentrator based on an 8x8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were done for 4 and 5 layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware have been successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency.

翻译：无触发数据采集系统（DAQ）需将多链路数据流传输至处理节点。短输入数据字必须被集中打包成输出接口（如PCI Express）使用的长位向量。在此过程中，需剔除无用数据，生成密集的有用DAQ数据流，同时保持数据的时间顺序。本文提出一种采用反向输出基线网络（BNRO）进行高速数据路由的新方案。通过深入分析网络操作，相比此前基于8×8网络的集中器，本方案显著提高了可扩展性。通过向BNRO网络添加额外层级即可实现扩展，同时最小化资源消耗。针对4层和5层（16输入与32输入）网络进行了仿真。针对16输入场景，成功完成了FPGA实现及实际硬件测试。每层可独立添加流水线寄存器，以缩短关键路径并提高最大可接受时钟频率。