The increasing transistor scale integration poses, among others, the thermal-aware floorplanning problem; consisting of how to place the hardware components in order to reduce overheating by dissipation. Due to the huge amount of feasible floorplans, most of the solutions found in the literature include an evolutionary algorithm for, either partially or completely, carrying out the task of floorplanning. Evolutionary algorithms usually have a bottleneck in the fitness evaluation. In the problem of thermal-aware floorplanning, the layout evaluation by the thermal model takes 99.5\% of the computational time for the best floorplanning algorithm proposed so far.The contribution of this paper is to present a parallelization of this evaluation phase in a master$-$worker model to achieve a dramatic speed-up of the thermal-aware floorplanning process. Exhaustive experimentation was done over three dimensional integrated circuits, with 48 and 128 cores, outperforming previous published works.

翻译：随着晶体管集成规模的不断增加，热感知布局规划问题日益凸显：即如何放置硬件组件以通过散热减少过热现象。由于可行布局方案数量庞大，现有文献中的多数解决方案采用进化算法来部分或完全执行布局规划任务。进化算法通常存在适应度评估的瓶颈。在热感知布局规划问题中，当前最优布局规划算法中热模型对布局的评估耗时占计算总时间的99.5%。本文的贡献在于提出了一种基于主从模型的评估阶段并行化方法，以显著加速热感知布局规划过程。在包含48核与128核的三维集成电路上进行了详尽的实验，其结果优于先前已发表的研究成果。