Physically Unclonable Functions (PUFs) are used for securing electronic devices across the implementation spectrum ranging from Field Programmable Gate Array (FPGA) to system on chips (SoCs). However, existing PUF implementations often suffer from one or more significant deficiencies: (1) significant design overhead; (2) difficulty to configure and integrate based on application-specific requirements; (3) vulnerability to model-building attacks; and (4) spatial locality to a specific region of a chip. These factors limit their application in the authentication of designs used in diverse applications. In this work, we propose MeLPUF: Memory-in-Logic PUF; a low-overhead, distributed PUF that leverages the existing logic gates in a design to create cross-coupled inverters (i.e., memory cells) in a logic circuit as an entropy source. It exploits these memory cells' power-up states as the entropy source to generate device-specific unique fingerprints. A dedicated control signal governs these on-demand memory cells. They can be dispersed across the combinational logic of a design to achieve distributed authentication. They can also be synthesized with a standard logic synthesis tool to meet the target area, power, and performance constraints. We evaluate the quality of MeLPUF signatures with circuit-level simulations and experimental measurements using FPGA silicon (TSMC 55nm process). Our analysis shows the high quality of the PUF in terms of uniqueness, randomness, and robustness while incurring modest overhead. We further demonstrate the scalability of MeLPUF by aggregating power-up states from multiple memory cells, thus creating PUF signatures or digital identifiers of varying lengths. Additionally, we suggest optimization techniques that can be leveraged to boost the performance of MeLPUF further.

翻译：物理不可克隆函数被广泛应用于从现场可编程门阵列到片上系统等不同实现层次的电子设备安全防护。然而，现有PUF实现普遍存在以下关键缺陷：（1）显著的设计开销；（2）难以根据特定应用需求进行配置与集成；（3）易受模型构建攻击；（4）局限于芯片特定区域的物理空间分布。这些因素限制了其在多样化应用场景设计认证中的适用性。本文提出MeLPUF：一种低开销、分布式的内存-逻辑物理不可克隆函数，通过利用设计中现有逻辑门构建逻辑电路中的交叉耦合反相器（即存储单元）作为熵源。该结构利用存储单元的上电状态生成设备特异性唯一指纹。专用控制信号可调控这些按需存储单元，并将其分散部署于组合逻辑电路中实现分布式认证。此类单元可通过标准逻辑综合工具进行综合，以满足目标面积、功耗与性能约束。我们通过电路级仿真及基于FPGA硅片（台积电55纳米工艺）的实验测量评估了MeLPUF签名质量。分析表明，该PUF在独特性、随机性与鲁棒性方面表现优异，且仅产生适度开销。通过聚合多个存储单元的上电状态生成不同长度的PUF签名或数字标识符，进一步验证了MeLPUF的可扩展性。此外，我们提出了可提升MeLPUF性能的优化技术。