Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology (UVM) is widely used in industry to improve verification efficiency through structured and reusable testbenches, constructing these testbenches and generating sufficient stimuli remain challenging. These challenges arise from the considerable manual coding effort required, repetitive manual execution of multiple EDA tools, and the need for in-depth domain expertise to navigate complex designs.Here, we present UVM^2, an automated verification framework that leverages Large Language Models (LLMs) to generate UVM testbenches and iteratively refine them using coverage feedback, significantly reducing manual effort while maintaining rigorous verification standards.To evaluate UVM^2, we introduce a benchmark suite comprising Register Transfer Level (RTL) designs of up to 1.6K lines of code.The results show that UVM^2 reduces testbench setup time by up to UVM^2 compared to experienced engineers, and achieve average code and function coverage of 87.44% and 89.58%, outperforming state-of-the-art solutions by 20.96% and 23.51%, respectively.

翻译：验证已成为集成电路（IC）开发的主要瓶颈，消耗近70%的总开发工作量。尽管通用验证方法学（UVM）通过结构化可重用测试平台在工业界被广泛用于提升验证效率，但构建此类测试平台及生成充足激励仍面临挑战。这些挑战源于大量手动编码需求、多个EDA工具的重复人工操作，以及驾驭复杂设计所需的深度领域专业知识。为此，我们提出UVM^2——一种利用大语言模型（LLM）自动生成UVM测试平台，并通过覆盖率反馈迭代优化的自动化验证框架，在维持严格验证标准的同时显著降低人工投入。为评估UVM^2，我们引入包含高达1.6K行代码的寄存器传输级（RTL）设计基准测试集。结果表明，相较于经验丰富的工程师，UVM^2可将测试平台搭建时间缩短至UVM^2，并分别实现87.44%的代码覆盖率和89.58%的功能覆盖率，较现有最优方案分别提升20.96%和23.51%。