Functional verification remains a critical bottleneck in modern IC development cycles, accounting for approximately 70% of total development time in many projects. However, traditional methods, including constrained-random and formal verification, struggle to keep pace with the growing complexity of modern semiconductor designs. While recent advances in Large Language Models (LLMs) have shown promise in code generation and task automation, significant challenges hinder the realization of end-to-end functional verification automation. These challenges include (i) limited accuracy in generating Verilog/SystemVerilog verification code, (ii) the fragility of LLMs when executing complex, multi-step verification workflows, and (iii) the difficulty of maintaining verification consistency across specifications, coverage models, and test cases throughout the workflow. To address these challenges, we propose UCAgent, an end-to-end agent that automates hardware block-level functional verification based on three core mechanisms. First, we establish a pure Python verification environment using Picker and Toffee to avoid relying on LLM-generated SystemVerilog verification code. Second, we introduce a configurable 31-stage fine-grained verification workflow to guide the LLM, where each stage is verified by an automated checker. Furthermore, we propose a Verification Consistency Labeling Mechanism (VCLM) that assigns hierarchical labels to LLM-generated artifacts, improving the reliability and traceability of verification. Experimental results show that UCAgent can complete end-to-end automated verification on multiple modules, including the UART, FPU, and integer divider modules, achieving up to 98.5% code coverage and up to 100% functional coverage. UCAgent also discovers previously unidentified design defects in realistic designs, demonstrating its practical potential.

翻译：功能验证仍是现代集成电路（IC）开发周期中的关键瓶颈，在众多项目中约占总体开发时间的70%。然而，包括约束随机验证和形式化验证在内的传统方法，已难以跟上现代半导体设计日益增长的复杂性。尽管最近大型语言模型（LLMs）在代码生成和任务自动化方面展现出潜力，但实现端到端功能验证自动化仍面临重大挑战，包括：(i) 生成的Verilog/SystemVerilog验证代码精度有限，(ii) LLMs在执行复杂多步骤验证工作流时的脆弱性，以及(iii) 在整个工作流中维持规范、覆盖模型与测试用例间验证一致性的困难。为应对这些挑战，我们提出UCAgent——一种基于三项核心机制实现硬件模块级功能验证自动化的端到端智能体。首先，我们利用Picker和Toffee构建纯Python验证环境，以避免依赖LLM生成的SystemVerilog验证代码。其次，我们引入可配置的31阶段细粒度验证工作流以引导LLM，其中每个阶段均由自动化检查器进行验证。此外，我们提出验证一致性标记机制（VCLM），为LLM生成的工件分配分层标签，从而提升验证的可靠性和可追溯性。实验结果表明，UCAgent能够在UART、FPU及整数除法器等多个模块上完成端到端自动化验证，代码覆盖率最高达98.5%，功能覆盖率最高达100%。同时，UCAgent还在实际设计中发现了此前未被识别的缺陷，展示了其实用潜力。