I present ARCS, a system for amortized analog circuit generation that produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combining two learned generators (a graph VAE and a flow-matching model) with SPICE-based ranking achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution is Group Relative Policy Optimization (GRPO): I identify a critical failure mode of REINFORCE (cross-topology reward distribution mismatch) and resolve it with per-topology advantage normalization, improving simulation validity by +9.6pp over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking. ARCS does not yet match the per-design quality of search-based optimization (5.48 vs. 7.48 reward), but its >1000x speed advantage enables rapid prototyping, design-space exploration, and warm-starting search methods (recovering 96.6% of GA quality with 49% fewer simulations).

翻译：本文提出ARCS系统，一种面向摊销式模拟电路生成的框架，可在毫秒级生成完整的SPICE可仿真设计（包括拓扑结构与元件参数），而无需传统搜索方法所需的分钟级时间。该系统融合两个学习型生成器（一个图变分自编码器与一个流匹配模型）与基于SPICE的排序校验，构建混合流水线，仅需8次SPICE评估即可在32种拓扑上实现99.9%的仿真有效性（奖励值6.43/8.0），其评估次数比遗传算法减少40倍。在单模型推理模式下，采用最佳三元候选选择的拓扑感知图Transformer在97毫秒内达到85%的仿真有效性，速度较随机搜索提升600倍以上。关键技术贡献在于组相对策略优化：本文识别出REINFORCE方法的根本失效模式（跨拓扑奖励分布失配），并通过基于拓扑的逐类优势归一化予以解决，在仅需500次强化学习步数（比REINFORCE减少10倍）的情况下将仿真有效性提升9.6个百分点。此外，通过拓扑感知词元掩码实现的文法约束解码从构造层面保证100%的结构有效性。尽管ARCS在单设计质量上尚未达到基于搜索优化的水平（奖励值5.48对7.48），但其超千倍的速度增益可支持快速原型设计、设计空间探索以及搜索方法的热启动（以49%更少的仿真次数恢复遗传算法96.6%的质量）。