This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation that produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combining two learned generators (a graph VAE and a flow-matching model) with SPICE-based ranking achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning, resolving a critical failure mode of REINFORCE (cross-topology reward distribution mismatch) through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.

翻译：本文提出了ARCS（自回归电路合成）系统，一种用于摊销式模拟电路生成的框架，能够在毫秒级时间内生成完整的、可进行SPICE仿真的设计（包含拓扑结构与元件参数），而基于搜索的方法通常需要数分钟。通过将两个学习型生成器（图变分自编码器与流匹配模型）与基于SPICE的排序相结合，混合流水线在仅使用8次SPICE评估的情况下，在32种拓扑上实现了99.9%的仿真有效性（奖励6.43/8.0），评估次数比遗传算法减少40倍。对于单模型推理，采用Best-of-3候选选择的拓扑感知图Transformer在97毫秒内达到85%的仿真有效性，速度比随机搜索提升超过600倍。关键的技术贡献在于将组相对策略优化（GRPO）适配至多拓扑电路强化学习场景，通过逐拓扑优势归一化解决了REINFORCE算法的关键失败模式（跨拓扑奖励分布失配）。这使得在仅500步强化学习训练（比REINFORCE减少10倍步数）中，仿真有效性相对REINFORCE提升9.6个百分点。基于语法约束的解码通过拓扑感知令牌掩码机制，从结构上保证了100%的结构有效性。