In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks. We first analyze the impact of the number of independent voltage islands on the resulting signal-to-noise ratio and trace misalignment. As part of our analysis of misalignment, we propose a novel unsupervised machine learning (ML) based attack that is effective on systems with three or fewer independent voltages. Our results show that iRDVS with four voltage islands, however, cannot be broken with 200k encryption traces, suggesting that iRDVS can be effective. We finish the talk by describing an iRDVS test chip in a 12nm FinFet process that incorporates three variants of an AES-256 accelerator, all originating from the same RTL. This included a synchronous core, an asynchronous core with no protection, and a core employing the iRDVS technique using asynchronous logic. Lab measurements from the chips indicated that both unprotected variants failed the test vector leakage assessment (TVLA) security metric test, while the iRDVS was proven secure in a variety of configurations.

翻译：本文描述并分析了一种基于岛的随机动态电压缩放（iRDVS）方法，以抵御功耗侧信道攻击。我们首先分析了独立电压岛数量对信噪比和迹线失准的影响。作为失准分析的一部分，我们提出了一种新颖的基于无监督机器学习（ML）的攻击方法，该方法对具有三个或更少独立电压的系统有效。然而，我们的结果表明，采用四个电压岛的iRDVS在20万次加密迹线下无法被攻破，这表明iRDVS具有有效性。我们最后描述了一款采用12nm FinFet工艺制造的iRDVS测试芯片，该芯片集成了三种AES-256加速器变体，均源自相同的RTL设计。这些变体包括一个同步内核、一个无保护的异步内核，以及一个采用异步逻辑实现iRDVS技术的内核。芯片的实验室测量结果表明，两种未受保护的内核均未通过测试向量泄漏评估（TVLA）安全度量测试，而iRDVS在各种配置下均被证明是安全的。