Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data movements. Even though most of the dynamic power consumption in SAs is due to multiplications and additions, pipelined data movement within the SA constitutes an additional important contributor. The goal of this work is to reduce the dynamic power consumption associated with the feeding of data to the SA, by synergistically applying bus-invert coding and zero-value clock gating. By exploiting salient attributes of state-of-the-art CNNs, such as the value distribution of the weights, the proposed SA applies appropriate encoding only to the data that exhibits high switching activity. Similarly, when one of the inputs is zero, unnecessary operations are entirely skipped. This selectively targeted, application-aware encoding approach is demonstrated to reduce the dynamic power consumption of data streaming in CNN applications using Bfloat16 arithmetic by 1%-19%. This translates to an overall dynamic power reduction of 6.2%-9.4%.

翻译：脉动阵列架构通过流水线化处理单元阵列，利用局部连接与预编排数据移动加速矩阵乘法运算。尽管脉动阵列中大部分动态功耗来源于乘法与加法运算，但阵列内的流水线数据移动同样是不可忽略的能耗来源。本研究旨在通过协同应用总线反转编码与零值时钟门控技术，降低数据输入脉动阵列所引发的动态功耗。通过利用先进卷积神经网络的特征属性（如权重的数值分布规律），所提脉动阵列仅对具有高翻转率的数据实施编码；当任一输入为零时，则完全跳过无效运算。实验表明，这种面向应用场景的选择性编码方法在使用Bfloat16算术的卷积神经网络应用中，可使数据流传输动态功耗降低1%-19%，对应整体动态功耗下降6.2%-9.4%。