While numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting Intellectual Property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an Integrated Circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of Length of Oxide Diffusion and Well Proximity Effect on transistors to fine-tune critical parameters such as transconductance (gm) and threshold voltage (Vth). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28nm and a 65nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an Operational Transconductance Amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130dB), phase margin (up to 50 degrees), 3dB bandwidth (approximately 2.5MHz), and power consumption (around 1mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead.

翻译：尽管数字域中有多种混淆技术可用于保护数字资产，但针对模拟域知识产权（IP）保护的关注却显著不足。这主要源于集成电路（IC）中模拟元件占比较小，芯片表面大部分区域用于数字模块。然而，尽管模拟元件面积较小，它们仍是极具价值的IP，亟需有效保护。本文提出一种突破性方法，通过利用IC设计中通常被视为不良效应的布局效应来保护模拟IP。具体而言，我们利用氧化物扩散长度和阱邻近效应对晶体管的影响，精细调节跨导（gm）和阈值电压（Vth）等关键参数。这些参数通过密钥输入隐藏，类似于数字IC中采用的逻辑锁定方法。本研究在两种商用CMOS工艺（28nm和65nm节点）中探索了布局效应的应用。为验证所提技术的有效性，我们将其应用于运算跨导放大器的锁定。通过施加大量密钥集（超过5万组和30万组）进行广泛仿真，评估混淆强度。结果表明，当使用错误密钥时，性能指标出现显著退化：开环增益（高达130dB）、相位裕度（高达50度）、3dB带宽（约2.5MHz）及功耗（约1mW）。研究结果凸显了本方法的优势及其伴随的开销。